CHARGE GAIN STRESS TEST CIRCUIT FOR NON-VOLATILE MEMORY AND CHARGE GAIN STRESS TEST METHOD

摘要

PROBLEM TO BE SOLVED: To provide a charge gain stress test circuit and a charge gain stress test method of a non-volatile memory for optimizing a charge gain stress test time without imposing any load on a peripheral circuit. SOLUTION: First, second, and third switches SW11, SW12, and SW13 are controlled by a first control signal READ and a second control signal ERASE, and the read operation and deleting operation of a flash memory cell 30 is repeatedly operated. Then, a stress voltage Vpps is applied to the gate terminal of the flash memory cell 30, and the compared result of cell currents Icell of the flash memory cell 30 with reference currents Iref is outputted as a signal SOUT.