首页> 外国专利> DIGITAL-TO-ANALOG CONVERTER (DAC) AND METHOD THAT PRODUCE AN APPROXIMATELY PIECEWISE LINEAR ANALOG WAVEFORM

DIGITAL-TO-ANALOG CONVERTER (DAC) AND METHOD THAT PRODUCE AN APPROXIMATELY PIECEWISE LINEAR ANALOG WAVEFORM

机译:数字到模拟转换器(DAC)和产生近似分段线性模拟波形的方法

摘要

A digital-to-analog converter (DAC), comprising: a plurality of waveform shaping circuits (100) that produce drive signals that switch during rise and fall times along rising (94) and falling (96) edges, respectively, between low and high plateaus (98) in response to waveform shaping circuits for a known clock period; a plurality of limiting switches (102) having transfer functions that limit the drive signals' low and high plateau values to low and high limiting values, respectively, while approximately maintaining the shape of the rising and falling edges; a weighting circuit (104) that weights the drive signals in accordance with their respecitve bits' positions in the codewords to produce weighted drive signals; and a summation circuit that sums the weighted drive signals to construct an analog waveform having output plateau values and rising and falling output edges, said waveform shaping circuits setting said rise and fall times so that the rising and falling output edges settle in rise and fall settling times Trs and Tfs, respectively, measured from successive clock edges of said digital signal to within a first error bound of a linear output ramp whose slope is a function of the difference between successive codewords, and said limiting switches setting the low and high limiting values so that the output plateau values settle in a settling time Tps measured from the end of said rise and fall times to within a second error bound of ideal values represented by the codewords so that the analog waveform more closely approximates a piecewise linear waveform, which has non-zero rise and fall times, than it does a zero-order-hold (ZOH) waveform to reduce spectral distortion in the analog waveform. 311 י" ג בתמוז התש" ס - July 16, 2000
机译:一种数模转换器(DAC),包括:多个波形整形电路(100),其产生驱动信号,该驱动信号在上升和下降时间期间分别沿上升沿(94)和下降沿(96)在低沿和下降沿之间切换。在已知的时钟周期内响应波形整形电路的高平稳区(98);具有传递函数的多个限位开关(102),其将驱动信号的低和高平稳值分别限制为低和高极限值,同时大致保持上升沿和下降沿的形状;加权电路(104),根据所述驱动信号在码字中的相应位的位置对驱动信号进行加权,以产生加权的驱动信号;以及一个求和电路,该求和电路对加权的驱动信号求和以构建具有输出平稳值和上升和下降输出边缘的模拟波形,所述波形整形电路设置所述上升和下降时间,以使上升和下降输出边缘稳定在上升和下降沉降中。从所述数字信号的连续时钟沿到线性输出斜坡的第一误差范围内测量的时间Trs和Tfs,所述线性输出斜坡的斜率是连续码字之间的差的函数,并且所述限位开关设置低和高极限值从而使输出平稳值稳定在一个稳定时间Tps内,该稳定时间从所述上升和下降时间的末尾到由码字表示的理想值的第二误差范围之内测得,以便模拟波形更接近于分段线性波形,非零上升和下降时间,而不是零阶保持(ZOH)波形,以减少模拟波形中的频谱失真R M。 311י"גבתמוזהתש"תש-2000年7月16日

著录项

  • 公开/公告号IL118277B

    专利类型

  • 公开/公告日2000-07-16

    原文格式PDF

  • 申请/专利权人 RAYTHEON COMPANY;

    申请/专利号IL118277

  • 发明设计人

    申请日1996-05-15

  • 分类号H03M1/00;H03M1/80;

  • 国家 IL

  • 入库时间 2022-08-22 01:56:04

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