A process for the manufacture of dual-voltage MOS transistors.

摘要

A method of forming a high voltage MOS and a low voltage MOS both having lightly doped drain structures comprises forming a first gate oxide layer (204a) in the region of the HV MOS, forming an overlaying gate oxide layer (206), depositing a polysilicon layer and then doping and etching to form gates (28, 210), performing a first dopant implant perpendicular to the substrate surface to form lightly doped regions (212, 214), covering the LV MOS with a photoresist (216), performing a large angle tilt implantation (#=15-60‹) to form a buffer region 218, removing the photoresist, forming sidewall spacers upon the gates 28, 210 and then implanting the high concentration low resistivity regions of both the HV and LV MOS. Dopant concentrations and doping energies are disclosed. The buffer region reduces hot-carrier effects.