IMPLEMENTATION ARCHITECTURE FOR PERFORMING HIERARCHICAL MOTION ANALYSIS OF IMAGES IN REAL TIME

摘要

First hardware means, comprising a given number ofprior-art image-pyramid stages (406-1, 406-n), together withsecond hardware means, comprising the same given number ofnovel motion-vector stages (416-1, 416-n), perform cost-effectivehierarchical motion analysis (HMA) in real time, with minimumsystem processing delay and/or employing minimum hardwarestructure. Specifically, the first and second hardware means, inresponse to relatively high-resolution image data from an ongoinginput series of successive given pixel-density image-data framesthat occur at a relatively high frame rate (e.g., 30 frames persecond), derives, after a certain processing-system delay, anongoing output series of successive given pixel-density vector-data frames that occur at the same given frame rate. Each vector-data frame is indicative of image motion occurring between eachpair of successive image frames.