Harvard superscalar computer architecture Multiplexed massively.

摘要

SE has a central processing unit (CPU) MASSIVELY MULTIPLEXING HAVING A plurality of independent computer circuits, A BUS OF INNER RESULTS SEPARATELY TO TRANSMIT THE RESULTING OUT OF EACH OF THESE computer circuits, and a plurality of registers GENERAL PURPOSE COUPLED EACH OF THE COMPUTER CIRCUITS. EACH OF RECORDS ARE GENERAL PURPOSE PORTS OF ENTRY multiplexed ARE CONNECTED TO EACH OF THE BUSES OF RESULTS. EACH OF THE GENERAL PURPOSE REGISTERS also has an output port that is connected to an input port MULTIPLEX OF AT LEAST ONE OF COMPUTER CIRCUITS. CIRCUITS EACH OF COMPUTING is dedicated to at least one mathematical function ONLY AND AT LEAST ONE OF THE CIRCUITS COMPUTING it includes at least one logic function. AT LEAST ONE OF THE CIRCUITS COMPUTING includes a plurality of processing circuits MATEMATICOSY LOGICOS ACTIONABLE CONCURRENT AND A output multiplexer to select one of THE RESULTING OUTPUT FOR YOUR BUS transmission on RESULTS. It also incorporates a CPU instruction word VERY LONG SERIES USING A LOCATION OF BITS ASSIGNED TO REPRESENT CODES FOR EACH SELECTION COMPONENTS CPU. SELECTION OF THESE CODES ARE SENT DIRECTLY TO EACH OF THE COMPONENTS CPU via a control circuit PROGRAM. Further it provides a CONTROL CIRCUIT IN A SEPARATE DATA STRUCTURE DESIGN FOR HARVARD CPU.