HIGH RESOLUTION DISPLAY CONTROLLER WITH REDUCED WORKING FREQUENCY REQUIREMENT FOR THE DISPLAY DATA HANDLING CIRCUITRY

摘要

Display controllers for flat panel usually comprise an A/D converter, a pixel processor (e.g. for performing scaling and dithering of the image) and a display memory controller. When, as requested with high display resolutions, such controllers have to work at high frequencies, they become complex and power consuming. Such problem is solved here by splitting the controller in two similar arrangements that work in parallel, e.g. one for even pixels in the pixel data stream and the other for odd pixels. By virtue of parallel working, the operating frequency of each arrangement is halved. Pixel processors in each of the two arrangements receive data from the A/D converters of both arrangements, which is necessary for most pixel operations. Possibly, also the display memory is split in even and odd memories. Both odd and even pixel data streams output by the controllers are then recombined and provided synchronously to the display panel.