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High temperature high voltage operation test mode (BURN-IN TEST MODE) entry improvement device of semiconductor device

机译:半导体器件的高温高压操作测试模式(BURN-IN TEST MODE)进入改善装置

摘要

The apparatus for improving the entry of the high temperature high voltage operation test mode of the semiconductor device is to detect the level of the substrate bias voltage of the semiconductor chip itself and prevent the entry into the high temperature high voltage operation test mode in an unstable state. In the apparatus for improving the entry of a high temperature high voltage operation test mode (Burn_In Test Mode) of a semiconductor device having a bias voltage generator, the level of the substrate bias voltage branched from the substrate bias voltage generator and a reference voltage level are compared. And a substrate bias voltage level sensing means for outputting a high temperature high voltage operation test disable signal, and a switching means for switching the high temperature high voltage operation test disable signal to block the high temperature high voltage operation test disable signal. It is composed.
机译:用于改善半导体器件的高温高压操作测试模式的进入的设备是检测半导体芯片本身的衬底偏置电压的电平,并且防止在不稳定的情况下进入高温高压操作测试模式的设备。州。在用于改善具有偏置电压产生器的半导体器件的高温高压操作测试模式(Burn_In测试模式)的进入的设备中,从衬底偏置电压产生器分支的衬底偏置电压的电平和参考电压电平比较。并且,衬底偏置电压电平感测装置用于输出高温高压操作测试禁用信号,以及开关装置,其用于切换高温高压操作测试禁用信号以阻断高温高压操作测试禁用信号。它是组成的。

著录项

  • 公开/公告号KR19990086723A

    专利类型

  • 公开/公告日1999-12-15

    原文格式PDF

  • 申请/专利权人 김영환;

    申请/专利号KR19980019836

  • 发明设计人 윤혁수;

    申请日1998-05-29

  • 分类号H01L21/66;

  • 国家 KR

  • 入库时间 2022-08-22 01:46:29

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