10/100 10/100 MB CLOCK RECOVERY ARCHITECTURE FOR SWITCHES REPEATERS AND MULTI-PHYSICAL LAYER PORTS

摘要

A clock recovery scheme is disclosed for recovering clock and serial data from an input data stream of a local area network station. A phase picker structure added by a phase interpolator is used as part of the clock recovery structure to improve phase resolution. A single clock generation module (CGM) and N phase multiplexers for each of the clock recovery channels on the chip are used to select one of the M phases of the CGM's 250 Mhz clock signal for each clock recovery channel. In order to provide the required phase resolution, a phase interpolator is used. The phase interpolator generates a number of delay steps at even intervals between the total phase steps of the phase multiplexer. Each phase multiplexer is preceded or delayed in response to a pumpup or pumpdn signal from each clock recovery channel (CRM).