首页> 外国专利> METHOD AND ARCHITECTURE FOR CALCULATING MAE IN A MOTION ESTIMATOR

METHOD AND ARCHITECTURE FOR CALCULATING MAE IN A MOTION ESTIMATOR

机译:在运动估计器中计算MAE的方法和体系结构

摘要

The present invention relates to an adder of a motion estimator, and more particularly, to an addition method and an adder structure for simplifying the interconnection of a pipelined adder to which a Wallace tree is applied. The matrix size is reduced in half by adding the matrix to the 4-input 2-output wallless tree. Divided into groups All intermediate result data were processed during the cycle, and the structure of the present invention is the first Wallace adder 40, the second Wallace adder 41, the third Wallace adder 42, and the fourth Wallace adder 43 ), A fifth Wallace adder 44, a sixth Wallace adder 45, a seventh Wallace adder 46, and a merge adder 47 for outputting an absolute error value MAE, and Two neighboring adder outputs from the stage wallless adder are input to the wallless adder of the next stage to simplify the interconnection between each module and reduce the number of hardware (wallis tree), thereby reducing chip area and cost in VLSI fabrication. This has the effect of being reduced.
机译:本发明涉及运动估计器的加法器,更具体地说,涉及用于简化应用了华莱士树的流水线加法器的互连的加法和加法器结构。通过将矩阵添加到4输入2输出无墙树中,矩阵大小减小了一半。分成几组在该循环中处理了所有中间结果数据,并且本发明的结构是第一华莱士加法器40,第二华莱士加法器41,第三华莱士加法器42和第四华莱士加法器43),第五华莱士加法器44,第六华莱士加法器45,第七华莱士加法器46和用于输出绝对误差值MAE的合并加法器47,并且来自级无壁加法器的两个相邻的加法器输出被输入到下一级的无壁加法器以简化。每个模块之间的互连,减少了硬件(瓦利斯树)的数量,从而减少了VLSI制造中的芯片面积和成本。这具有减少的效果。

著录项

  • 公开/公告号KR100236033B1

    专利类型

  • 公开/公告日1999-12-15

    原文格式PDF

  • 申请/专利权人 DAEWOO ELECTRONICS CO.LTD;

    申请/专利号KR19960072053

  • 发明设计人 이수정;

    申请日1996-12-26

  • 分类号G06F7/50;

  • 国家 KR

  • 入库时间 2022-08-22 01:46:19

相似文献

  • 专利
  • 外文文献
  • 中文文献
获取专利

客服邮箱:kefu@zhangqiaokeyan.com

京公网安备:11010802029741号 ICP备案号:京ICP备15016152号-6 六维联合信息科技 (北京) 有限公司©版权所有
  • 客服微信

  • 服务号