Control circuit for column address strobe delay in SDRAM has control circuit unit for generating four control signals for controlling latches and data selector

摘要

The control circuit has a control circuit unit for generating four control signals for controlling latches and data selector The circuit has a control circuit unit (21) for receiving a clock signal (QCLK) and supplying data and four control signals. A latch (22) supplies or stores internal data based on the first control signal (con3). A second latch operates based on the second control signal. A data selector (25) directly routes the internal data or the data from the second latch based on the fourth control signal. A third latch (24) supplies data from the selector to a data output buffer or feeds the data from the selector based on the third control signal. An Independent claim is included for a control circuit.