Interrupt controller for microcontroller unit with fast response after interrupt generation

摘要

An interrupt instruction register (17) receives the interrupt signals from the interrupt mask circuit, determines the priorities at the instruction of the interrupt priority register (15), and transfers them to an interrupt pin of a CPU. An interrupt status register (19) delivers information regarding a register select signal (IIR-SEL), interrupt instruction register (21) stores branching instructions received from the CPU and delivers an interrupt instruction to the CPU based on the register select signal. A bus interface circuit (18) is provided for input/output of an address signal between the CPU and the interrupt controller.