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computer architecture with mehrfachbefehlsausgabe
computer architecture with mehrfachbefehlsausgabe
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机译:具有多个命令输出的计算机体系结构
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摘要
A system for issuing a family of instructions during a single clock includes a decoder for decoding the family of instructions and logic, responsive to the decode result, for determining whether resource conflicts would occur if the family were issued during one clock. If no resource conflicts occur, an execution unit executes the family regardless of whether dependencies among the instructions in the family exist.
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