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Cascode circuit with high output impedances for the operation with a low supply voltage

机译:具有高输出阻抗的共源共栅电路,可在低电源电压下运行

摘要

PURPOSE: To provide a cascode circuit capable of lowering the lower limit value of an operating voltage in a CMOS process and enlarging output signal amplitude by responding to input signals supplied from an input terminal and raising the margin of the output signal amplitude obtained from an output terminal by a negative feedback means. ;CONSTITUTION: This circuit is provided with the serial connection circuit of transistors 1 and 2 serially connected between the output terminal 71 and a lower side power-supply potential, the input terminal 70 connected to the gate electrode of the transistor 1, the transistor 3 gate-grounded by a direct connection point and a current mirror circuit composed of the transistor 4 and 5 in the relation of reverse polarity with the transistors 1, 2 and 3 to which a current is supplied from a higher side power supply VDD. Then, the cascode circuit is provided with the negative feedback loop of a gain first stage. Thus, the drain current of the transistor determined by the voltage supplied to the voltage input terminal 70 is hardly influenced by the DC potential of the current output terminal 71. Thus, the output impedance of the cascode circuit is raised.;COPYRIGHT: (C)1995,JPO
机译:目的:提供一种共源共栅电路,该共源共栅电路能够响应于从输入端子提供的输入信号并降低从输出获得的输出信号幅度的裕度,从而降低CMOS工艺中的工作电压的下限值并增大输出信号幅度。终端通过负反馈手段。 ;构成:该电路具有串联连接在输出端子71和下侧电源电位之间的晶体管1和2的串联连接电路,输入端子70连接到晶体管1,晶体管3的栅极。通过直接连接点和由晶体管4和5组成的电流镜电路以与晶体管1、2和3的极性相反的栅极栅极接地,并且从较高侧电源VDD向其提供电流。然后,共源共栅电路具有增益第一级的负反馈回路。因此,由提供给电压输入端子70的电压确定的晶体管的漏极电流几乎不受电流输出端子71的DC电势的影响。因此,共源共栅电路的输出阻抗升高。 1995年,日本特许厅

著录项

  • 公开/公告号DE69421775T2

    专利类型

  • 公开/公告日2000-07-13

    原文格式PDF

  • 申请/专利权人 NEC CORP. TOKIO/TOKYO;

    申请/专利号DE1994621775T

  • 发明设计人 ETOH TOSHIYUKI;

    申请日1994-09-13

  • 分类号H03F1/22;

  • 国家 DE

  • 入库时间 2022-08-22 01:40:39

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