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METHOD FOR MANUFACTURING BICMOS INTEGRATED CIRCUITS ON A CLASSIC CMOS SUBSTRATE

机译:在经典CMOS基板上制造BICMOS集成电路的方法

摘要

P The invention relates to a method for manufacturing a BICMOS integrated circuit comprising an NPN transistor in a heavily P-type wafer (42) and coated with a lightly doped P-type layer (41), comprising forming a collector N (43) of a bipolar transistor; coating the structure with a priming layer of polycrystalline silicon (52) and opening above portions of manifold boxes; growing undoped and then doped P-type silicon to form a monocrystalline base region; deposit an insulating layer (61) and open it; depositing N-type emitter polycrystalline silicon (62) and etching it outside the useful zones; etch the base silicon outside the useful zones; forming spacers (72, 71, 73); and form a collector contact area (75) at the same time as the drain implantation of the N-channel MOS transistors. /P
机译:本发明涉及一种用于制造BICMOS集成电路的方法,该BICMOS集成电路在重度P型晶片(42)中包括NPN晶体管,并涂覆有轻掺杂的P型层(41),包括形成集电极N(43 )的双极晶体管;在结构上涂上一层多晶硅底漆(52),并在歧管箱的上方开口;生长未掺杂然后掺杂的P型硅以形成单晶基极区;沉积绝缘层(61)并打开它;沉积N型发射极多晶硅(62)并在有用区域之外对其进行蚀刻;蚀刻有用区域之外的基础硅;形成垫片(72、71、73);并在N沟道MOS晶体管的漏极注入的同时形成集电极接触区(75)。

著录项

  • 公开/公告号FR2786608A1

    专利类型

  • 公开/公告日2000-06-02

    原文格式PDF

  • 申请/专利权人 STMICROELECTRONICS SA;FRANCE TELECOM;

    申请/专利号FR19980015239

  • 发明设计人 MICHEL LAURENS;

    申请日1998-11-30

  • 分类号H01L21/8249;

  • 国家 FR

  • 入库时间 2022-08-22 01:39:38

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