Multiple input zero power AND/NOR gate for use in a field programmable gate array (FPGA)

摘要

A zero power AND or NOR (AND/NOR) gate includes circuitry configured for use in a field programmable gate array (FPGA). The AND/NOR gate includes multiple driver circuits each receiving a single input of the AND/NOR gate, each driver circuit being connected by a NORCNTL line and a NOROUT line to a current switch circuit. The NOROUT line provides the output of the AND/NOR gate, while the NORCNTL line enables zero power operation. The driver circuits can be included in input/output buffers (IOBs), configurable logic blocks (CLBs), or other components throughout an FPGA to receive more inputs than typically provided to a single CLB. Each of the driver circuits includes a pull down transistor having a gate receiving an input signal (IN.sub.1 -IN. sub.N) of the AND/NOR gate, and having a source to drain path connecting the NOROUT line to Vss. The current switch circuit includes a current source and a current control transistor with a source to drain path connecting the current source to the NOROUT line, and a gate coupled by the NORCNTL line to the driver circuits. Additional circuitry in each of the driver circuits controls the NORCNTL line to enable the current control transistor to turn on for a predetermined period of time when an input signal (IN.sub.1 -IN.sub.N) is applied to a driver circuit to turn off its respective pull down transistor.