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Mac processor with efficient Viterbi ACS operation and automatic traceback store
Mac processor with efficient Viterbi ACS operation and automatic traceback store
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机译:具有高效Viterbi ACS操作和自动回溯存储功能的Mac处理器
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摘要
A dual-MAC processor optimized so that two Viterbi ACS operations, including traceback bit storage, can be executed in two machine cycles is disclosed. The processor comprises a pair of adder arithmetic logic units connected to a common accumulator register bank and supporting full and split-mode add, subtract, and compare operations. Viterbi compare operations are executed using the subtract function and the sign bit is combined with a compare mode bit to generate a traceback output which indicates the proper traceback bit to store. When a compare operation is performed and a Viterbi mode bit is active, each generated traceback output is shifted into a traceback register for later use in a Viterbi traceback routine.
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