CMOS implemented output buffer circuit for providing ECL level signals

摘要

A CMOS implemented output buffer (10) provides ECL level output signals. The output buffer (10) is implemented in two stages. The first stage (36) includes an inverter having a resistor (39) in series with a P- channel transistor (38) and an N-channel transistor (40) and provides the initial buffering. The resistor (39) in the first inverter stage (36) is used to reduce a cross-over current in the second drive stage (42). The second stage (42) provides additional drive capability and includes an integral level converter. The integral level converter is implemented as a P-channel transistor (44) connected in series with the P- channel and N- channel output driver transistors (53 and 55). The P- channel transistor (44) provides the level shifting function to ECL levels for the second stage. The bias level of the P-channel transistor (44) determines the output logic swing.