A level linearizer in which higher bits are used to select upper and lower values for a level control signal and lower bits for interpolation

摘要

Received signal strength in a CDMA mobile phone receiver may be obtained by averaging the sum of the squares of the I and Q components output from the demodulator (this calculation increases power consumption so an approximation may be used). A linearizer (18) (figure 1) is used to ensure linearity of the input to the A/D converter (14). An output from the linearizer (18) is also supplied to adder (9) where it is combined with a command from the base station to provide a signal to the linearizer 1 for the transmitter. In figure 2 which, represents linearizers 1 and 18, 8-bit input data is divided into upper bit values and lower bit values. The upper bit values address ROM 101 which outputs upper and lower values representing control voltages (see fig. 3) to selectors 105 and 106. These are latched in 107 and 108 before being added and halved in circuit 110 to produce an average. The selectors 105 and 106 are meanwhile switched to receive the outputs of selectors 111 and 112. The lower bit values are selected by selector 104. If the first lower bit is 1 the selector 111 takes the output from latch 107. If the first lower bit is 0 the output from the half circuit 110 is taken. If the first lower bit is 0 the selector 112 takes the output from latch 108. If the first lower bit is 1 the output from the half circuit 110 is taken. By repeating the averaging process for all the lower bits and the newly latched values the final interpolated value for the control voltage is determined. Temperature compensation may also be provided.