A direct-sequence spread-spectrum receiver

摘要

Circuitry, termed herein "Lag Lock Loop", is a direct-sequence spread-spectrum receiver function to synchronise a locally generated code sequence with a received signal by generating the local code at a fixed rate (10, 12, 22) while applying a variable delay 26 to the received signal 15 to achieve synchronisation. This arrangement simplifies the means generating the local code as it can simply run at a fixed rate. The variable delay 26 is positioned prior to the despreading means 18 and out of the frequency and phase lock loop 20.