System for providing high performance speculative processing of complex load/store instructions by generating primitive instructions in the load/store unit and sequencer in parallel

摘要

One aspect of the invention relates to a method for operating a superscalar processor having an instruction cache, a sequencing unit, a load/store unit, a cache, an architectural register file and a rename register file. In one particular version of the invention, the method includes the steps of forwarding an instruction from the instruction cache to the sequencing unit operable to access multiple architectural registers; generating a plurality of primitive instructions responsive to the forwarded instruction in which an individual primitive instruction is operable to access an individual architectural register; and sequentially issuing the primitive instructions to move data between the data cache and the rename register file.