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Cache memory device and method for providing concurrent independent multiple accesses to different subsets within the device

机译:高速缓冲存储器设备和用于提供对设备内不同子集的并发独立多重访问的方法

摘要

A multi-access method which is applied to a cache memory device interposed between a processor and a storage device, for enabling multi- access. When two or more access requests are received, a plurality of pairs (each pair composed of a data array and a tag array) are divided into two or more non-overlapping subsets, and each of the subsets is supplied with information which specifies data to be accessed and is input in conjunction with each access request, whereby accesses are performed in parallel in accordance with the access requests. This multi- access method is applicable to a cache memory used in a high-performance parallel-processing architecture including a few processors having a common cluster.
机译:一种多址访问方法,该方法应用于插入在处理器和存储设备之间的高速缓存存储设备,以实现多址访问。当接收到两个或更多个访问请求时,多个对(每个对由一个数据数组和一个标记数组组成)被分成两个或更多个不重叠的子集,并且每个子集都提供有指定数据的信息,以供与每个访问请求一起被输入并被访问,从而根据访问请求并行地执行访问。这种多址访问方法适用于在高性能并行处理体系结构中使用的高速缓存存储器,该体系结构包括几个具有公用群集的处理器。

著录项

  • 公开/公告号US6038647A

    专利类型

  • 公开/公告日2000-03-14

    原文格式PDF

  • 申请/专利权人 FUJITSU LIMITED;

    申请/专利号US19960662010

  • 发明设计人 MASAYUKI SHIMIZU;

    申请日1996-06-12

  • 分类号G06F12/08;

  • 国家 US

  • 入库时间 2022-08-22 01:37:37

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