System for operating a universal asynchronous receiver/transmitter (UART) at speeds higher than 115,200 bps while maintaining full software and hardware backward compatibility

摘要

A method and apparatus for increasing the speed of a Universal Asynchronous Receiver/Transmitter ("UART") while maintaining backward compatibility. The UART contains registers for controlling the flow of data. Two registers are the DLL (Divisor Latch Least significant) internal register and the DLM (Divisor Latch Most significant) internal register. Due to the UART not using all of the 16 bits contained in the DLL and DLM registers, an additional register, the Increased Baudrate (IB) register, is created. The IB register uses bits which are unused (or always set to zero in a conventional UART). Through the IB register, the UART may use higher crystal frequencies. In addition, when the UART is at speeds equal to or less than 115,200 bits per second, the IB register is programmed to zero, thus mimicking the operation of a convention UART at speeds equal to or less than 115,200 bits per second. Thus, the method and system for a high speed UART increases speeds while still maintaining backward compatibility.