首页> 外国专利> Circuit and method for implementing single-cycle read/write operation(s), and random access memory including the circuit and/or practicing the method

Circuit and method for implementing single-cycle read/write operation(s), and random access memory including the circuit and/or practicing the method

机译:用于实现单周期读/写操作的电路和方法,以及包括该电路和/或实施该方法的随机存取存储器

摘要

A circuit including an address bus providing random addresses for a random access memory array, and a register configured to receive, store or transfer (i) a first random address from the address bus in response to a first periodic signal transition and (ii) a second random address from the address bus in response to a second periodic signal transition, wherein the first and second periodic signal transitions occur within a single periodic signal cycle, and are preferably complementary to each other. In a further embodiment, the invention concerns a random access memory having an address bus providing random address information for a random access memory array, a predecoder configured to at least partially decode the random address information from the address bus, a register configured to receive, store or transfer (i) a first at least partially decoded random address from the address bus in response to a first periodic signal transition and (ii) a second at least partially decoded random address from the address bus in response to a second periodic signal transition, wherein the first and second periodic signal transitions occur within a single periodic signal cycle; and a postdecoder configured to activate the random addresses in the random access memory in response to receiving the random addresses from the register.
机译:一种电路,包括:地址总线,其为随机存取存储器阵列提供随机地址;以及寄存器,其被配置为响应于第一周期性信号转变而从地址总线接收,存储或传输(i)第一随机地址;以及响应于第二周期信号转变而来自地址总线的第二随机地址,其中第一和第二周期信号转变发生在单个周期信号周期内,并且优选地彼此互补。在另一个实施例中,本发明涉及一种具有地址总线的随机存取存储器,该地址总线提供用于随机存取存储器阵列的随机地址信息;预解码器,被配置为至少部分地解码来自该地址总线的随机地址信息;寄存器,被配置为接收:存储或传输(i)响应于第一周期性信号转变而从地址总线传输的第一至少部分解码的随机地址和(ii)响应于第二周期性信号转变而从地址总线传输的第二至少部分解码的随机地址,其中第一和第二周期信号转变发生在单个周期信号周期内;后解码器,被配置为响应于从寄存器接收到随机地址而激活随机存取存储器中的随机地址。

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