Circuit for allowing a two-pass fuse blow to memory chips combining an array built-in self-test with redundancy capabilities

摘要

A circuit that enhances the testability of an integrated circuit of a memory type and which identifies defective redundant word lines in a state of the art SRAM macro that combines an ABIST structure with a redundancy mechanism. The circuit allows a two-pass fuse blow after completing the burn-in process that significantly increases the manufacturing yield and repairability of the SRAM macro.