首页> 外国专利> Dynamic allocation and reallocation of buffers in links of chained DMA operations by receiving notification of buffer full and maintaining a queue of buffers available

Dynamic allocation and reallocation of buffers in links of chained DMA operations by receiving notification of buffer full and maintaining a queue of buffers available

机译:通过接收缓冲区已满的通知并维护可用缓冲区的队列,在链接的DMA操作的链接中动态分配和重新分配缓冲区

摘要

A system which performs chained direct memory access (DMA) operations, includes a working set of buffers, a first-in-first-out memory, a first DMA co-processor, a second DMA co-processor and a controlling processor. The working set of buffers are available for receiving data from chained DMA operations. The first-in-first-out memory store addresses of buffers, from the working set of buffers, which are available for immediate allocation. The first DMA co-processor and the second DMA co-processor perform the chained DMA operations. The controlling processor sets up the chained DMA operations and adds addresses of free buffers to the first-in- first-out memory. When performing a first chained DMA operation, the first DMA co-processor accesses the first-in-first-out memory to allocate for itself a first buffer from the queue of buffers when a first link in the first chained DMA operation requires a buffer. When the first buffer is filled, the first DMA co-processor immediately notifies the controlling processor. When performing a second chained DMA operation, the second DMA co- processor accesses the first-in-first-out memory to allocate for itself a second buffer from the queue of buffers when a first link in the second chained DMA operation requires a buffer. When the second buffer is filled, the second DMA co-processor immediately notifies the controlling processor.
机译:一种执行链式直接存储器访问(DMA)操作的系统,包括一组工作缓冲区,一个先进先出存储器,一个第一DMA协处理器,一个第二DMA协处理器和一个控制处理器。缓冲区的工作集可用于从链接的DMA操作接收数据。先进先出存储器存储来自缓冲区工作集的缓冲区地址,这些地址可立即分配。第一DMA协处理器和第二DMA协处理器执行链接的DMA操作。控制处理器设置链接的DMA操作,并将空闲缓冲区的地址添加到先进先出存储器中。当执行第一链式DMA操作时,当第一链式DMA操作中的第一链接需要缓冲区时,第一DMA协处理器访问先进先出存储器以从缓冲区队列中为其分配第一缓冲区。当第一缓冲区已满时,第一DMA协处理器立即通知控制处理器。当执行第二链式DMA操作时,当第二链式DMA操作中的第一链路需要缓冲区时,第二DMA协处理器访问先进先出存储器以从缓冲区队列中为其分配第二缓冲区。当第二个缓冲区已满时,第二个DMA协处理器立即通知控制处理器。

著录项

  • 公开/公告号US6092127A

    专利类型

  • 公开/公告日2000-07-18

    原文格式PDF

  • 申请/专利权人 HEWLETT-PACKARD COMPANY;

    申请/专利号US19980080058

  • 发明设计人 ERIC GREGORY TAUSHECK;

    申请日1998-05-15

  • 分类号G06F13/10;G06F12/02;

  • 国家 US

  • 入库时间 2022-08-22 01:36:37

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