Satellite payload processing system providing on-board rate alignment

摘要

A rate alignment apparatus for a satellite includes an on- board clock, an input switch, an output switch and a ping-pong buffer pair including first and second buffers and connected to the input switch and the output switch. The first and second buffers receive a stream of digital baseband symbols recovered from an uplink signal depending on the operation of the input switch and the output switch. The first buffer of the buffer pair receives the bits in accordance with an uplink clock rate obtained from the uplink signal. The second buffer of the buffer pair substantially simultaneously empties the stored contents thereof to a third buffer in accordance with the on-board clock, the operations of the first and second buffers being reversed upon actuation of the input switch and the output switch. First and second correlators generate a spike when a header denoting when a frame in the stream of baseband symbols is detected. The buffer pair is operable to continue to write the stream of baseband symbols into one of the buffer pair until the spike occurs. The input switch and the output switch are switched to their reverse states, and the first and second buffers the uplink signal are read to the output thereof in accordance with the on-board clock rate. A sychronized pulse oscillator connected to the first and second correlators generates a smoothed pulse for each of the symbols read to the output. A counter connected to the oscillator counts the smoothed pulses. A number of bits is added to or removed from the headers of the streams in accordance with the value of the counter.