Efficient back bias (V.sub.BB) detection and control scheme for low voltage DRAMS

摘要

An efficient back bias (V.sub.BB) detection and control circuit make possible a low voltage memory device and includes an on-chip V.sub. BB level sensor (38) that includes a dynamic voltage reference shift circuit (40, 42, 44, 46) for establishing a first voltage level (-(. vertline.2 VTP|+VTN)) during power-up and a second voltage level (-. vertline.2 VTP| during normal operation. The first voltage level is of a deeper level for achieving a short power-up interval. The second voltage level has a level less deep than said first voltage for achieving low power operation.