DMA control apparatus for multi-byte serial-bit transfer in a predetermined byte pattern and between memories associated with different asynchronously operating processors for a distributed system

摘要

A DMA control apparatus transfers a data set of bytes, with no intermixing these data bytes and with favorable efficiency. A DMA controller receives data bytes serially and writes this data to a RAM. At this time, when the serially sent data are taken to be made up of data sets where one information item is formed of two bytes, the DMA controller, while temporarily storing data received in odd-numbered order in a data-set adjusting register, controls block write of this together with data received in even-numbered order to the RAM. Due to this, access where data other than these data sets is intermixed is eliminated, even in a case where asynchronous word-unit access of the RAM is performed by the CPU.