Cache coherency controller of cache memory for maintaining data anti- dependence when threads are executed in parallel

摘要

Disclosed is a cache coherency controller used in a multi- processor system. The cache coherency controller reflects a cache line including data produced by a preceding thread to a cache line including data produced by a succeeding thread. On the other hand, the cache coherency controller prevents a cache line including data produced by the succeeding thread from being reflected to the cache line including data produced by the preceding thread. The cache coherency controller maintains a sequential order (relationship) among threads based on a thread sequence information table and thereby maintains data anti- dependence.