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Encoding and decoding rate-1/n convolutional codes and their punctured versions

机译:编码和解码速率为1 / n的卷积码及其删余版本

摘要

The present invention is directed to the encoding and decoding of a digital signal. The encoding process results in a rate-1/n convolutional code derived from a rate-1/2 convolutional code. The process includes: selecting a base convolutional encoding rate of rate- 1/l, where l is an integer; selecting an output encoding rate of 1/n, where n is an integer greater than 1; encoding an input digital signal into a convolutional code comprised of signals S(0) through S(l-1), the convolutional code having the rate 1/l convolutional code encoding rate; and providing a rate-1/n convolutional code, which is derived from the rate-1/l convolutional code, the rate-1/n convolutional code having N(i) copies of the rate-1/l signals S(i), where i is from 0 through 1-l and where the sum of N(i) is equal to n. The decoding process results in a digital signal estimated from received symbols which include rate-1/n convolutional code generated by the above encoding process and any noise that may have been introduced by a transmission medium. The process includes the step of: generating a signal pair from the received symbols, the signal pair having a first signal and a second signal which are suitable for decoding by a rate-1/2 convolutional decoder. The first signal is an average of a sum of encoded signals which correspond to positions in the rate-1/2 convolutional code encoded using a first generator polynomial. The second signal is an average of a sum of encoded signals which correspond to positions in the rate-1/n convolutional code encoded using a second generator polynomial. The method also includes a step of decoding the signal pairs using a rate- 1/2 convolutional decoder.
机译:本发明针对数字信号的编码和解码。编码过程导致从比率1/2卷积码得出的比率1 / n卷积码。该过程包括:选择速率为1 / l的基本卷积编码速率,其中l为整数;以及选择1 / n的输出编码率,其中n是大于1的整数;将输入的数字信号编码成由信号S(0)至S(1-1)组成的卷积码,该卷积码具有1/1的卷积码编码率;并且提供从速率1 / l卷积码导出的速率1 / n卷积码,速率1 / n卷积码具有速率1 / l信号S(i)的N(i)个副本,其中i从0到1-l,并且N(i)的总和等于n。解码过程导致从接收到的符号中估计出数字信号,该数字符号包括由上述编码过程生成的速率1 / n卷积码以及传输介质可能引入的任何噪声。该过程包括以下步骤:从接收到的符号生成信号对,该信号对具有适合于速率1/2卷积解码器解码的第一信号和第二信号。第一信号是与使用第一生成多项式编码的1/2速率卷积码中的位置相对应的编码信号之和的平均值。第二信号是与使用第二生成多项式编码的比率1 / n卷积码中的位置相对应的编码信号之和的平均值。该方法还包括使用速率1/2卷积解码器对信号对进行解码的步骤。

著录项

  • 公开/公告号US6134696A

    专利类型

  • 公开/公告日2000-10-17

    原文格式PDF

  • 申请/专利权人 LSI LOGIC CORPORATION;

    申请/专利号US19980087459

  • 发明设计人 ADVAIT MOGRE;ROBERT MORELOS-ZARAGOZA;

    申请日1998-05-28

  • 分类号H03M13/03;

  • 国家 US

  • 入库时间 2022-08-22 01:35:54

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