Program possible logical array and the array logic which are combined

摘要

(57) Abstract As for PLD, entry being joint possible choice in the entry line and output has joint possible 1st program possible AND array choice in 2nd program possible OR array. This PLD, furthermore, entry being joint possible choice in the entry line, and has the 3rd program possible AND array where output is jointed to 4th fixed OR array fixed. Aforementioned 2nd OR array is jointed to also aforementioned 4th OR array fixed. As for this circuit layout, as the both some weak points of normal PAL and PLA architecture are overcome, the majority of that and the like merits is maintained.