Bit phase simulation circuit and bit phase simulation device

摘要

PROBLEM TO BE SOLVED: To stably output data latched in a most proper timing with respect to data and a clock signal whose mutual phase relation is unknown. SOLUTION: A pulse width generating circuit 1 makes a pulse width of input data of an NRZ signal from a data input terminal 0 narrow and provides an output of a 1st pulse width signal, a 2nd pulse width signal and delayed data delaying input data by a prescribed time. Even when mutual phase relation between the input data and n-phases clocks ϕ1 to ϕn being 1/n equal divisions of one clock width of the input data is unknown, shift registers 41 to 4n are used to match the top and the tail end to absorb phase fluctuation in m-bit width and data latched and outputted by latch timing decesion circuits 21 to 2n and phase align circuits 31 to 3n in the most proper timing are outputted stably from a selector 6 synchronously with the clock ϕ1.