2-bit non-volatile Electrically Curry erasable programmable semiconductor memory cell utilizing asymmetrical charge trapping

摘要

Capable of storing non-volatile Electrically Curry erasable programmable read only memory (57) [Abstract] Disclosed herein is a (EEPROM) two bits of information. This 2-bit EEPROM is provided with a dielectric film as the charge trapping layer of non-conductive, the dielectric film can be formed, for example, a silicon nitride film. The dielectric film is sandwiched between the silicon oxide film two which functions as an insulating film. The present invention includes a method of erasing the writing of this two-bit EEPROM device, and read. Dielectric film of non-conducting, functions as a charge trapping media. Conductive gate layer is formed and on top of the silicon oxide film on the upper side. A right bit left bits are stored in two places apart in the charge trapping layer in the left bit is formed at a position close to the left area of ​​the memory cell, the right bit position close to the right area of ​​the memory cell It is formed in the. The writing of bits of each of the memory device, by using a hot-electron writing method is to perform a write general manner, ie, by applying a write voltage to the gate, the left and right regions applying a write voltage to another area of ​​either one, is carried out by the ground area of ​​the other. Hot electrons are sufficiently accelerated is injected to the area to write the voltage of the charge trapping layer is applied. On the other hand, it is to perform in the opposite direction to the writing direction, that is, by applying a read voltage to the gate, reading of the memory device, reading another area of ​​one of the left area and right area applying a voltage, is carried out by the ground area of ​​the other. Set relatively low gate voltage, and the reading and writing of two bits is possible because it is because it is to perform the opposite direction reading. Accordingly, the voltage acting across the charge trapping region is reduced significantly. In addition, the effect of charge that is trapped in the charge trapping region confined by it, corresponding to each bit is amplified, the write time is reduced significantly. Furthermore, from the charge trapping region of the nitride film corresponding to the area for applying the erasing voltage to the gate, by applying the erase voltage to another area of ​​one of the left and right regions, was applied to the voltage By discharging the electrons, it is possible to perform individual erase of two bits of the memory cell.