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Record the wiring storage Characteristic evaluation program in printed circuit board designing record media and the device

机译:在印刷电路板设计记录介质和设备中记录布线存储的特性评估程序

摘要

PROBLEM TO BE SOLVED: To increase the evaluating speed of the wiring laying space of a printed board. ;SOLUTION: The wiring laying space of a printed board is evaluated in such a way that parts are arranged on the board by inputting the connected relations (pin pairs) between the parts and the pins of the parts and grouping a plurality of parts from the positional relation and connected relation among the arranged parts. Then a group shape containing the parts in the above group is generated and pin pairs which are connected from a certain group to other groups are extracted. In addition, the passing points (passing pins) of the wires of the number of the pin pairs are generated on the group shape and the connections among the virtual pins are generated as the connection information among the groups. Finally, the wiring spaces (expressed by the ratios of the areas of conductor sections, such as pins, wires to the area of the external shape of the board) in the groups and among the groups are calculated.;COPYRIGHT: (C)2000,JPO
机译:要解决的问题:提高评估电路板布线空间的速度。 ;解决方案:通过输入零件和零件的销之间的连接关系(销对),并从零件中组合多个零件,来评估印刷电路板的布线空间,以便将零件布置在板上。布置部分之间的位置关系和连接关系。然后,生成包含上述组中各部分的组形状,并提取从某个组连接到其他组的引脚对。另外,在组形状上生成多个引脚对的导线的通过点(通过引脚),并且将虚拟引脚之间的连接生成为组之间的连接信息。最后,计算出各组之间以及各组之间的布线空间(用引脚,导线等导体部分的面积与板的外形面积之比表示).COPYRIGHT:(C)2000 ,日本特许厅

著录项

  • 公开/公告号JP3166847B2

    专利类型

  • 公开/公告日2001-05-14

    原文格式PDF

  • 申请/专利权人 日本電気株式会社;

    申请/专利号JP19980322053

  • 发明设计人 涌井 章;

    申请日1998-11-12

  • 分类号G06F17/50;

  • 国家 JP

  • 入库时间 2022-08-22 01:34:18

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