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Burn-in test jig for semiconductor device and burn-in test method

机译:半导体器件的老化测试夹具和老化测试方法

摘要

PROBLEM TO BE SOLVED: To provide a jig and method for performing burn-in test on semiconductor device by which the deformation of solder balls can be suppressed when burn-in tests are performed on a semiconductor device, even when eutectic solder is used for securing the mountability of the semiconductor device. SOLUTION: A jig for performing burn-in test on semiconductor device comprises a substrate 2 which is interposed between a semiconductor device 7 and an anisotropic conductive sheet 4, and contact sections 3 which are integrally formed with the substrate 2 through the substrate 2 and are made of a conductive material and into which ball grids 8 are inserted. The jig is constituted in such a way that the ball grids 8 are pressed against the electrode sections 5 of the conductive sheet 4 through the contact sections 3.
机译:解决的问题:提供一种用于在半导体器件上进行老化测试的夹具和方法,通过该夹具和方法,即使在使用共晶焊料进行固定的情况下,在半导体器件上进行老化测试时,也可以抑制焊球的变形。半导体器件的可安装性。解决方案:用于在半导体器件上执行老化测试的夹具包括:衬底2,其插在半导体器件7和各向异性导电片4之间;以及接触部分3,其通过衬底2与衬底2整体形成,并形成接触。由导电材料制成并且插入有球栅8。夹具以如下方式构成:将球栅8通过接触部3压在导电片4的电极部5上。

著录项

  • 公开/公告号JP3189812B2

    专利类型

  • 公开/公告日2001-07-16

    原文格式PDF

  • 申请/专利权人 日本電気株式会社;

    申请/专利号JP19980336473

  • 发明设计人 松岡 洋;

    申请日1998-11-12

  • 分类号G01R31/26;H01L21/60;

  • 国家 JP

  • 入库时间 2022-08-22 01:34:05

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