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Lead end grid array semiconductor package using the same grid and array-type lead frame

机译:使用相同栅格和阵列型引线框架的引线端栅格阵列半导体封装

摘要

PROBLEM TO BE SOLVED: To reduce noise and increase the speed of signal transmission by making the lead ends constituting one end of leads constitute a grid array on the same plane within a certain lower region corresponding to the mounting region of a semiconductor chip. ;SOLUTION: In a lead 2 extended in X-axis direction, a direction converting lead part 2' is made on the same plane, and in a lead 2 extended in Y-axis direction, the ones where the direction converting lead parts 2' on the same plane are not made and the ones where they are made two or six are positioned alternately, and at each corner part, one lead end 4 is formed of two leads 2. The lead end 4 constitutes a grid array of alternate lateral row and longitudinal rows, being positioned in the specified position decided in advance on the same plane within a certain lower region corresponding to a semiconductor chip mounting region. Hereby, the signal transmission speed is increased by reducing the noise generated by signal interference phenomena.;COPYRIGHT: (C)1998,JPO
机译:解决的问题:通过使构成引线一端的引线端在与半导体芯片的安装区域相对应的某个下部区域内的同一平面上构成栅格阵列,来减少噪声并提高信号传输的速度。 ;解决方案:在X轴方向上延伸的引线2中,将方向转换引线部分2'制作在同一平面上,在Y轴方向上延伸的引线2中,将方向转换引线部分2'制作在同一平面上不在同一平面上,而是交替制作两个或六个平面,并且在每个角部,一个引线端4由两个引线2形成。引线端4构成交替的横向行的网格阵列纵列和纵列分别位于与半导体芯片安装区域相对应的某个下部区域内的同一平面上预先决定的指定位置。因此,通过减少信号干扰现象产生的噪声,可以提高信号传输速度。;版权所有:(C)1998,日本特许厅

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