首页> 外国专利> MATCHING METHOD OF HIGH-VOLTAGE ELEMENT AND LOW- VOLTAGE ELEMENT UTILIZING TRENCH ISOLATION STRUCTURE IN MANUFACTURE OF TRANSISTOR ELEMENT

MATCHING METHOD OF HIGH-VOLTAGE ELEMENT AND LOW- VOLTAGE ELEMENT UTILIZING TRENCH ISOLATION STRUCTURE IN MANUFACTURE OF TRANSISTOR ELEMENT

机译:晶体管元件制造中利用沟槽隔离结构的高电压元件和低电压元件的匹配方法

摘要

PROBLEM TO BE SOLVED: To increase a current and voltage drive capabilities and to cope with the demand of the matching of high-voltage and low-voltage elements by covering a channel region and the upper section of a partial dielectric region in a gate region formed by forming and etching a gate layer and forming source-drain regions, using the gate region and the dielectric region as masks.;SOLUTION: Drift regions 15 are formed to the sidewalls and surfaces of the lower sections of trench regions by ion implantation, using the nitride film of a semiconductor substrate 11 as a main body, and oxide films are formed on the sidewalls and surface of the bottom sections of the trench regions. The nitride film and a sacrificial oxide film are removed, the oxide film is thermoformed to the surface layer of the semiconductor substrate 11, two well regions are defined, N-type ion implantation and a standard annealing process are advanced and two N-type well regions 18 are formed. The oxide film is removed, and one gate oxide film 19 and N-type-doped polysilicon 20 are formed on the upper layer of the semiconductor substrate 11. Lastly, N+-doped polysilicon and N+ source 21 and drain 22 are formed by thermal diffusion or by ion implantation.;COPYRIGHT: (C)2001,JPO
机译:要解决的问题:通过在形成的栅极区域中覆盖沟道区域和部分介电区域的上部,来提高电流和电压驱动能力并满足高压和低压元件匹配的需求通过使用栅极区和介电区作为掩模,形成和蚀刻栅极层并形成源极-漏极区;解决方案:通过离子注入,利用离子注入在沟槽区下部的侧壁和表面上形成漂移区15。半导体基板11的氮化膜作为主体,氧化膜形成在沟槽区域的底部的侧壁和表面上。去除氮化膜和牺牲氧化膜,将氧化膜热成型到半导体衬底11的表面层,限定两个阱区,进行N型离子注入和标准退火工艺,并且进行两个N型阱形成区域18。去除氧化膜,并且在半导体衬底11的上层上形成一个栅氧化膜19和N型掺杂的多晶硅20。最后,通过热扩散形成N +掺杂的多晶硅以及N +源极21和漏极22。或通过离子注入。;版权所有:(C)2001,日本特许厅

著录项

  • 公开/公告号JP2001015734A

    专利类型

  • 公开/公告日2001-01-19

    原文格式PDF

  • 申请/专利权人 UNITED MICROELECTRONICS CORP;

    申请/专利号JP19990173027

  • 发明设计人 TO MEISHU;

    申请日1999-06-18

  • 分类号H01L29/78;H01L21/76;

  • 国家 JP

  • 入库时间 2022-08-22 01:31:19

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