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METHOD OF EXTRACTING CIRCUIT PARAMETERS, AND METHOD OF AND APPARATUS FOR DESIGNING SEMICONDUCTOR INTEGRATED CIRCUIT

机译:提取电路参数的方法,以及设计半导体集成电路的方法和装置

摘要

PROBLEM TO BE SOLVED: To enable highly precise calculation of finished wiring width and highly precise circuit simulation.;SOLUTION: Correlation data 101 between the distance between model wiring and wiring existing around the model wiring in the same layer and the difference between the mask-layout width and the finished width of the model wiring are prepared, the wiring length and wiring width of analyzing wiring and the distance between the analyzing wiring and the wiring existing around the analyzing wiring in the same layer are extracted from the actual layout 100 (102), and wiring resistance value and wiring capacitance value with respect to the extracted layout-wiring width of the analyzing wiring and the extracted distance between the analyzing wiring and the wiring existing around the analyzing wiring are calculated by using finished wiring width obtained by referring to the correlation data (105).;COPYRIGHT: (C)2001,JPO
机译:解决的问题:为了能够高精度地计算出完成的布线宽度并进行高精度的电路仿真。解决方案:模型布线之间的距离与同一层中模型布线周围存在的布线之间的距离以及掩模之间的差异之间的相关性数据101准备样版布线的版图宽度和最终宽度,从实际版图100中提取分析布线的布线长度和布线宽度以及同一层中分析布线与分析布线周围存在的布线之间的距离(102 ),并通过参考以下公式获得的最终布线宽度来计算相对于所提取的分析布线的布图布线宽度以及所分析的布线与存在于分析布线周围的布线之间的距离的布线电阻值和布线电容值。相关数据(105)。;版权:(C)2001,日本特许厅

著录项

  • 公开/公告号JP2001230323A

    专利类型

  • 公开/公告日2001-08-24

    原文格式PDF

  • 申请/专利权人 MATSUSHITA ELECTRIC IND CO LTD;

    申请/专利号JP20000035267

  • 发明设计人 ISHIKURA SATOSHI;

    申请日2000-02-14

  • 分类号H01L21/82;G03F1/08;G06F17/50;H01L21/027;

  • 国家 JP

  • 入库时间 2022-08-22 01:30:28

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