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INVERSE ELEMENT ARITHMETIC UNIT ON FINITE FIELD AND METHOD THEREFOR

机译:有限域上的逆元算术单元及其方法

摘要

PROBLEM TO BE SOLVED: To make an inverse element arithmetic performable at a high speed by reducing the number of memory accesses. ;SOLUTION: This inverse element arithmetic unit 10 is provided with a memory 19 storing a value performing an inverse element arithmetic and the value of the result of a concerned inverse element arithmetic, a square calculating circuit 11, a multiplying circuit 12, a first selector 16 selectively outputting one value of the value stored in the memory 19, a value from the square calculating circuit 11 and a value from the multiplying circuit 12, a second selector 17 selectively outputting either the value stored in the memory 19 or the value from the circuit 12, a third selector 18 selectively outputting either of inputted values to the circuit 12, a first register 13 which stores a value from the first selector 16 and outputs it to the circuit 11, the circuit 12 and the memory 19, a second register 14 which stores a value to be outputted from the second selector 17 and outputs it to the third selector 18 and a third register 15 which preserves a value to be outputted from the memory 19 during the inverse element arithmetic and outputs it to the selector 18.;COPYRIGHT: (C)2001,JPO
机译:解决的问题:通过减少存储器访问的数量,使逆元素算术可以高速执行。 ;解决方案:该逆元算术单元10设有存储器19,该存储器存储执行逆元算术的值和相关逆元算术的结果的值,平方计算电路11,乘法电路12,第一选择器。在图16中,有选择地输出存储器19中存储的值的一个值,平方计算电路11的值和乘法电路12的值,第二选择器17有选择地输出存储在存储器19中的值或来自乘法器12的值。电路12,第三选择器18有选择地将输入值输出到电路12,第一寄存器13和第二寄存器,第一寄存器13存储来自第一选择器16的值并将其输出到电路11,电路12和存储器19在图14中,其存储要从第二选择器17输出的值并将其输出到第三选择器18和第三寄存器15,第三寄存器15保留要从存储器1输出的值9在逆元算术期间,并将其输出到选择器18 。;版权:(C)2001,JPO

著录项

  • 公开/公告号JP2001034168A

    专利类型

  • 公开/公告日2001-02-09

    原文格式PDF

  • 申请/专利权人 TOYO COMMUN EQUIP CO LTD;

    申请/专利号JP19990204171

  • 发明设计人 YANAGISAWA SHIGEKI;

    申请日1999-07-19

  • 分类号G09C1/00;G06F7/00;G06F17/10;

  • 国家 JP

  • 入库时间 2022-08-22 01:27:30

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