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Updating condition status register based on instruction specific modification information in set/clear pair upon instruction commit in out-of-order processor
Updating condition status register based on instruction specific modification information in set/clear pair upon instruction commit in out-of-order processor
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机译:在无序处理器中提交指令时,基于置位/清除对中指令特定的修改信息更新条件状态寄存器
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摘要
A processor including a register, an execution unit, a temporary result buffer, and a commit function circuit. The register includes at least one register bit and may include one or more sticky bits. The execution unit is suitable for executing a set of computer instructions. The temporary result buffer is configured to receive, from the execution unit, register bit modification information provided by the instructions. The temporary result buffer is suitable for storing the modification information in set/clear pairs of bits corresponding to respective register bits of the register. The commit function circuit is configured to receive the set/clear pairs of bits from the temporary result buffer when the instruction is committed. The commit function circuit is suitable for generating an updated bit in response to receiving the set/clear pairs of bits. The updated bit is then committed to the corresponding register bit of the register.
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