首页> 外国专利> Narrow band-pass tuned resonator filter topologies having high selectivity, low insertion loss and improved out-of band rejection over extended frequency ranges

Narrow band-pass tuned resonator filter topologies having high selectivity, low insertion loss and improved out-of band rejection over extended frequency ranges

机译:窄带通调谐谐振器滤波器拓扑,在扩展的频率范围内具有高选择性,低插入损耗和改善的带外抑制性能

摘要

A tuned resonator circuit topology is disclosed that permits implementation of narrow band-pass filters having high loaded Q and optimal coupling (for low insertion loss) using a parallel tuned resonator topology at freqencies in the 1 to 2 GHz range and beyond. The topology consists of a mirror image of the parallel tuned circuit about the signal line of a conventional parallel tuned circuit to effect a cancellation of virtually all of the induced currents between the inductive elements of the resonators. This reduction in induced currents reduces the magnetic coupling between the resonators, thereby offsetting the increase in overall coupling between the resonators as frequency increases, and thereby serves to maintain optimal coupling between the resonators as the frequency of operation increases. Moreover, the mirror image topology increases the parallelism between the inductive elements in the resonators, thereby decreasing the inductance values and permitting an increase in capacitance values. Increasing the capacitancevalues of the resonators effectively offsets the decrease in the loaded Q as frequency is increased. The topology works for any number of parallel resonators. As the resolution of the manufacturing process decreases (e.g. from printed circuit board to integrated circuit processes), the range of operating frequencies scales with the increase in resolution.
机译:公开了一种调谐谐振器电路拓扑,该谐振器电路拓扑允许使用并行调谐谐振器拓扑在1至2 GHz范围及更高频率下实现具有高负载Q和最佳耦合(用于低插入损耗)的窄带通滤波器。该拓扑结构由并联调谐电路的镜像围绕常规并联调谐电路的信号线组成,以实现谐振器电感元件之间几乎所有感应电流的抵消。感应电流的这种减小减小了谐振器之间的磁耦合,从而抵消了随着频率增加谐振器之间的整体耦合的增加,从而随着工作频率的增加而保持了谐振器之间的最佳耦合。此外,镜像拓扑增加了谐振器中电感元件之间的平行度,从而减小了电感值并允许增加了电容值。随着频率的增加,增加谐振器的电容值可以有效抵消负载Q的减小。该拓扑可用于任意数量的并联谐振器。随着制造工艺的分辨率降低(例如,从印刷电路板到集成电路工艺),工作频率范围会随着分辨率的提高而缩放。

著录项

  • 公开/公告号AU1935200A

    专利类型

  • 公开/公告日2001-04-30

    原文格式PDF

  • 申请/专利权人 BROADBAND INNOVATIONS INC.;

    申请/专利号AU20000019352

  • 发明设计人 BRANISLAV PETROVIC;

    申请日1999-12-06

  • 分类号H03H7/09;H03H7/01;

  • 国家 AU

  • 入库时间 2022-08-22 01:21:16

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