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METHOD AND ARCHITECTURE FOR OPTIMIZING DATA THROUGHPUT IN A MULTI-PROCESSOR ENVIRONMENT USING A RAM-BASED SHARED INDEX FIFO LINKED LIST
METHOD AND ARCHITECTURE FOR OPTIMIZING DATA THROUGHPUT IN A MULTI-PROCESSOR ENVIRONMENT USING A RAM-BASED SHARED INDEX FIFO LINKED LIST
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机译:使用基于RAM的共享索引FIFO链接列表在多处理器环境中优化数据吞吐量的方法和体系结构
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摘要
A method and architecture for optimizing data throughput in a multiprocessor environment makes use of a RAM-based, shared index FIFO linked list, in which data to be processed is written to a central buffer and the index FIFO, constituting a linked list of indexes to the buffered data is passed between processing units within the system, providing a substantial reduction in the gate count required for processing the data. Messages are written to a central buffer; a linked list of indexes to the messages is created, and then pipelined to a processing unit as an index FIFO, so that the processor reads the entries of the linked list in sequence; as the entries are read, a message indicated by the entry is processed. Entries are enqueued and dequeued in an index FIFO RAM, so that enqueuing and dequeuing are performed in a single cycle with a single write operation.
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