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Dynamic random access memory circuit having a testing system and method to determine the sensitivity of a sense amplifier

机译:具有确定灵敏放大器灵敏度的测试系统和方法的动态随机存取存储器电路

摘要

A dynamic random access memory (DRAM) utilizes a testing system to independently control a voltage differential appearing between a pair of bit lines and sensed by the sense amplifier. The sensitivity of the sense amplifier is determined by monitoring an input/output signal in response to sensing the known voltage differential. The magnitude of the voltage differential appearing between the bit lines is controlled by enabling a first dummy cell to transfer a first reference charge onto a first bit line and by enabling a second dummy cell to transfer a second reference charge onto a second bit line.
机译:动态随机存取存储器(DRAM)利用测试系统来独立控制出现在一对位线之间并由感测放大器感测到的电压差。通过响应于感测已知电压差而监视输入/输出信号来确定感测放大器的灵敏度。通过使第一虚拟单元能够将第一参考电荷转移到第一位线上并通过使第二虚拟单元能够将第二参考电荷转移到第二位线上来控制出现在位线之间的电压差的大小。

著录项

  • 公开/公告号EP1045397A3

    专利类型

  • 公开/公告日2000-12-06

    原文格式PDF

  • 申请/专利权人 STMICROELECTRONICS INC.;

    申请/专利号EP20000302532

  • 发明设计人 BRADY JAMES;

    申请日2000-03-28

  • 分类号G11C29/00;G11C7/14;G11C7/24;G01R31/00;

  • 国家 EP

  • 入库时间 2022-08-22 01:17:56

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