Polarimetric detection processing circuit for a radar receiver

摘要

The processor includes a polarimetric constant false alarm rate detector which is positioned at the output of a target detector. A polarimetric clutter rejection filter is connected in parallel with the detector and is associated with the constant false alarm rate detector provided with the output of the target detector. A bank of polarimetric filters is placed in series with a second constant false alarm rate detector as the input to an OR-gate. A selection circuit (61) determines the Stokes' vector components and activates the clutter rejection filter. The bank of filters is inhibited when the degree of noise polarisation passes a threshold and reverses its action below the threshold which lies between 0.6 and 0.8, notably 0.68.