Mechanism for load block on store address generation and universal dependency vector/queue entry

摘要

A processor (10) comprising:   a dependency vector generation unit (134) configured to generate a dependency vector (80) corresponding to an instruction operation; and characterized by:   an instruction queue (36A) coupled to receive said dependency vector (80) and said instruction operation, wherein said instruction queue (36A) is configured to store said instruction operation and said dependency vector and is further configured to inhibit scheduling of said instruction operation until each dependency indicated within said dependency vector (80) is satisfied, and wherein said dependency vector is capable of indicating dependencies upon each other instruction operation within said instruction queue (36A), and wherein said dependency vector (80) comprises an indication corresponding to each of a plurality of queue entries within said instruction queue, and wherein said dependency comprises an ordering dependency.