CIRCUIT FOR STABLY GENERATING BANK SELECTION SIGNAL AND FOR ACQUIRING MARGIN BETWEEN COLUMN-ACTIVE CLOCK SIGNAL AND BANK ADDRESS

摘要

PURPOSE: A circuit is provided to stably generate a bank selection signal and to acquire a margin between a column-active clock signal and a bank address. CONSTITUTION: The device includes a bank-address input part(20), the first delay part(30), the second delay part(40) and a bank-selection signal enable part(50). The bank-address input part(20) receives an address(CAiB) of a selected bank. The first delay part(30) delays a low-active signal(PYE) due to a low-active command for activating memory cells of a word line direction. The second delay part(40) delays a column-active clock signal(PCLKD) due to a column-active command for activating memory cells of a bit line direction. The bank-selection signal enable part(50) generates a bank-selection signal(PCSLEB) according to the bank address(CAiB), the low-active signal(PYE), the column-active clock signal(PCLKD) and the delayed low-active signal(PYEB).