SENSE AMP PREVENTING BIT LINE DISTURB OF FLASH MEMORY

摘要

PURPOSE: A sense amp preventing a bit line disturb of a flash memory is provided to reduce a data error rate by reading data of a cell by applying a minimum voltage to a bit line using a voltage drop circuit to minimize a read disturb phenomenon, and to perform a long time read operation during a continuous read operation, and to reduce the memory size by not using a reference cell. CONSTITUTION: The sense amp includes a decoder part, an internal flash memory, a voltage drop circuit, a sense amp part and an output port. The sense amp part includes: voltage feedback N-MOS transistors(N11,N12,N14) feeding back a voltage shown sequentially during reading data stored in the internal flash memory to a chip read enable signal stage(EN); a P-MOS transistor(P1) switching a power supply voltage(VCC) and applying it to a node(Node1); an inverter(INV1) switching logically an input voltage level of an amplifier(14B) in case that there is data in a cell or there is no data in the cell; an inverter(INV2) inverting a chip read enable signal inputted to the chip read enable signal stage and inputting it to an N-MOS transistor(N13) controlling a gate voltage of the N-MOS transistor(N12); and the amplifier amplifying an output of the inverter(INV1).