The memory has a plurality of word lines WL1-8, a plurality of bit lines BL1-512 and BLa1-32, and a plurality of memory cells C1-512 and Ca1-32, and memory cells C1-512 and Ca1. Each of -32 is connected between the selected one of the word lines WL1-8 and the selected one of the bit lines BL1-512 and BLa1-32, and a plurality of connected to the selected one of the word lines WL1-8. The memory cells C1-512 and Ca1-32 are divided into a first group memory cell C1-512 and a second group memory cell Ca1-32, and the first group memory cells C1-512 are data. The second group memory cells Ca1-32 are provided for storage and are provided to store attribute data of the first group memory cells C1-512.
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