A HIERARCHICAL BUS SIMPLE COMA ARCHITECTURE FOR SHARED MEMORY MULTIPROCESSORS

摘要

The present invention is a shared-memory multiprocessor relates to a method of maintaining cache coherence (cache coherency) in a system, where each node itself is a shared memory multiprocessor having a plurality of nodes. In the present case, if the additional shared owner state (shared owner state) is held issues a read or write request to the highest cache level of the cache system in the cache memory for the top level in the system to miss the cache line (miss), owner of the cache line places the cache line on a bus interconnecting the cache memory of the top-level.