The present invention relates to digital audio interface circuits. The circuit comprises: a first multiplexer for selecting and outputting normal or reverse digital audio data according to a selection signal; a shift register for latching an output of the first multiplexer according to a load signal and shifting it in synchronization with a serial clock signal; A delay unit for delaying the most significant bit of the shift register by one clock according to a mode signal, an address generator for generating an address in synchronization with a sample frequency clock signal, and a least significant bit for the address in synchronization with the serial clock signal; After delaying two clocks, a word select signal generator for selectively outputting a delayed signal or an inverted delay signal according to the mode signal, and adjusting the generation time of a word select signal according to the mode signal to output as the load signal. It comprises a control unit. According to the present invention, both I2S and regular serial audio formats can be accommodated and data width can be adjusted.
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